I. Field of the Disclosure
The technology of the disclosure relates to memory controllers providing an interface to memory systems in computer systems.
II. Background
Microprocessors perform computational tasks in a wide variety of applications. A typical microprocessor application includes one or more central processing units (CPUs) that execute software instructions. The software instructions may instruct a CPU to fetch data from a location in memory, perform one or more CPU operations using the fetched data, and generate a result. The result may then be stored in memory. As non-limiting examples, this memory can be a cache local to the CPU, a shared local cache among CPUs in a CPU block, a shared cache among multiple CPU blocks, or main memory of the microprocessor.
In this regard, FIG. 1 is a schematic diagram of an exemplary system-on-a-chip (SoC) 10 that includes a CPU-based system 12. The CPU-based system 12 includes a plurality of CPU blocks 14(1)-14(N) in this example, wherein ‘N’ is equal to any number of CPU blocks 14(1)-14(N) desired. In the example of FIG. 1, each of the CPU blocks 14(1)-14(N) contains two CPUs 16(1), 16(2). The CPU blocks 14(1)-14(N) further contain shared Level 2 (L2) caches 18(1)-18(N), respectively. A shared Level 3 (L3) cache 20 is also provided for storing cached data that is used by any of, or shared among, each of the CPU blocks 14(1)-14(N). An internal system bus 22 is provided to enable each of the CPU blocks 14(1)-14(N) to access the shared L3 cache 20 as well as other shared resources. Other shared resources accessed by the CPU blocks 14(1)-14(N) through the internal system bus 22 may include a memory controller 24 for accessing a main, external memory (e.g., double-rate dynamic random access memory (DRAM) (DDR) provided in a dual in-line memory module (DIMM), as a non-limiting example), peripherals 26, other storage 28, an express peripheral component interconnect (PCI) (PCI-e) interface 30, a direct memory access (DMA) controller 32, and/or an integrated memory controller (IMC) 34.
As CPU-based applications executing in the CPU-based system 12 in FIG. 1 increase in complexity and performance, memory capacity can be a constraint. However, providing additional memory capacity in a CPU-based system increases costs and area needed for memory on an integrated circuit (IC). For example, if a CPU-based system, such as the CPU-based system 12 in FIG. 1, were provided in an SoC, such as the SoC 10, adding additional memory capacity may increase the SoC packaging. Data compression may be employed to increase the effective memory capacity of a CPU-based system without increasing physical memory capacity. Data compression can also be employed to increase memory access bandwidth between a memory controller and memory.
For example, data for a write operation in the CPU-based system 12 in FIG. 1 can be compressed, and the memory controller 24 may be configured to compress the data according to a defined compression algorithm. The compressed data is then written in compressed form at the data address in memory for the write operation. When a read operation is performed by the memory controller 24, the memory controller 24 needs to be able to determine if the data stored at the accessed data address in memory is stored in compressed or uncompressed form. In this regard, a data indicator may be provided that is associated with the data address in memory. In this manner, the memory controller 24 can consult the data indicator for a read operation for a given data address to determine if the read data should be uncompressed. However, providing additional data indicators associated with the data addresses in memory increases memory size. Also, if it is desired to read the data indicator in the same burst as the data at a given data address, the memory data bus width between the memory controller 24 and memory would have to be increased, which may be undesirable.
It is desirable to provide for storing and accessing an indicator, such as a data indicator, in association with memory in a compressed memory system to determine if read data is compressed or uncompressed as an example, without expanding memory size and without increasing the width of a memory data bus.